As a conventional clock-synchronization type semiconductor memory device, for example, an FCRAM (registered trademark), which is an asynchronous SRAM type fast access memory having a burst read mode, has come into practical use for mobile telephones which are recently in increasing demand.
The FCRAM, when it is set in the burst read mode, operates in synchronization with a clock signal externally input. The FCRAM outputs data when a number of clock pulses corresponding to a previously set latency have been input since input of an address.
In a continuous burst read mode in which a batch read data length is not specified, when a read address reaches a row address boundary of a memory array during continuous read, data output delay occurs. In order to notify the outside of this output delay, a data bus state signal indicating whether a data bus is valid or invalid is output from the FCRAM. A host apparatus can prevent erroneous read of invalid data by performing data read when the data bus state signal is at a level indicating “valid” (see, for example, Non-Patent Document 1).
FIG. 20 is a timing chart of a conventional clock-synchronization type semiconductor memory device, showing transition timings of an external input clock signal, an output data signal, a data bus state signal, and the like during burst read. In FIG. 20, /CE indicates a chip enable signal, ADD indicates an external input address signal, a CLK indicates an external input clock signal, a DQ indicates an output data signal, and /WAIT indicates a data bus state signal. Note that, in FIG. 20, it is assumed that the latency=4. Also, in FIG. 20 and the following description, numerals added to “CLK” indicate clock numbers which are counted after the start of a read operation.
In FIG. 20, a read address is input by ADD with respect to the rise of CLK1 after a predetermined setup time. Thereafter, CLK2 to CLK4 corresponding to a set clock number which is the latency−1 (i.e., 4−1=3 clocks) are input before DQ is output with CLK5. A /WAIT signal goes from an “L (Low)” level indicating that the data bus is invalid to a “H (High)” level indicating that the data bus is valid, with CLK4 which is one clock before the DQ is output.
It is assumed that, when four pieces of data have read out, a read address reaches a row address boundary of a memory array. In this case, four clocks after the /WAIT signal goes to “H”, the /WAIT signal goes to the “L” level indicating that the data bus is invalid. The following data is output after the /WAIT signal goes to the “H” level again.
Thus, when valid data is output, the /WAIT signal is caused to go to “H”, while when data is invalid, the /WAIT signal is caused to go to “L”. Thereby, the host apparatus is prevented from reading out erroneous data.
Also, a DDR SDRAM has come into practical use which is a memory for a high-speed system and outputs data at both edges of a clock. This DDR SDRAM is provided with a DQS (data strobe) terminal so as to achieve high speed, thereby avoiding an error in data reception.
In this memory, during write, a host apparatus outputs DQS and data synchronous with the DQS, while the memory takes in write data using the DQS.
During read, the memory outputs DQS and data synchronous with the DQS, while a host apparatus takes in read data using the DQS. The timing of outputting read data is determined, depending on a previously set latency. The DQS goes from HiZ (high-impedance state) to the “L” level, as preamble, one cycle before data is output. During the next cycle, the DQS goes to the “H” level, so that data output is started (e.g., Elpida Memory, Inc., “512M bits DDR SDRAM DATA SHEET”, Document No. E0699E50 (Ver. 5.0), November 2006, p. 27).
Non-Patent Document 1: FUJITSU, Ltd., “FUJITSU semiconductor device DATA SHEET DS05-11429-2 (Memory Mobile FCRAM MB82DBS02163C)”, 2005